1. Technical Field of the Invention
The present invention generally relates to methods for testing network devices, and in particular to methods for faster testing of read and write processes involving memory registers of network devices.
2. Description of the Related Art
Network interfaces for connecting a device, such as a computer, to a network, commonly include a media access controller (MAC) and a physical layer device (“PHY” or “PHY device”). The MAC ensures that data being sent is properly formatted and addressed, so that the frames or packets are properly recognized by other devices on the network. Signals from the MAC are sent to the PHY, which handles the actual transmission of signals on the network medium. The network medium may be any of a variety of well known media, such as fiber-optic cables or various types of dedicated metal-wire cables such as twisted shielded pair, 10 BASE-T, and wiring for telephone lines. Alternatively, the network medium may include wireless communication.
It is desirable for the interface between the MAC and the PHY to be independent of the type of network media to which the PHY is attached. Media independence of the interface between the MAC and PHY allows use of identical MACs with various types of PHYs. Such a media independent interface (MII) is described in IEEE Standard 802.3u-1995, which is incorporated herein by reference in its entirety.
IEEE Standard 802.3u-1995 provides that read and write operations to memory registers of a PHY may be performed by sending management data frames to the PHY through the MII via a management data input/output (MDIO) pin of the device. The management data frames include an indication of whether a read or write operation is to be performed, the address of the memory register to be read from or written to, and (for write operations) the data to be written to the memory register.
During the manufacture of network components or devices, such as the PHY device described above, the components are tested at various stages. Manufacturers have significant economic incentive to detect and discard faulty components as early in the manufacturing process as possible.
Network components are generally produced in large quantities. To rapidly test large quantities of components, automatic test equipment (generally “testers”) are used. The tester is electrically coupled to the inputs and outputs, such as the input and output pins, of a network component. The tester rapidly generates input signals for application to the integrated circuit of the network component, and can determine whether the appropriate response signals are generated. Because testers are highly automated, they can be programmed to run through a series of millions of test cases.
Testing of a PHY device involves the tester initiating numerous reads and writes to the memory registers of the PHY. Unfortunately, the management data frames for these test operations are serially passed through the MDIO pin at the relatively low rate of 2.5 Mb/sec, this rate being set by the management data clock rate of 2.5 MHz, which is specified in the IEEE 802.3u-1995 standard.
It would be desirable to increase the speed of testing of a PHY device which has a MII in accordance with the IEEE 802.3u-1995 standard.